Memory devices are typically provided in many data processing systems as semiconductor integrated circuits and/or external removable devices in computers or other electronic devices. There are many different types of memory including Random Access Memory (RAM), Read Only Memory (ROM), Dynamic Random Access Memory (DRAM), Synchronous DRAM (SDRAM), flash memory, and resistance variable memory, among others.
Conventional memory systems typically consist of one or more memory devices, such as DRAMs, mounted on a Printed Circuit Board (PCB) called a Dual In-line Memory Module (DIMM). The memory system is in communication with a memory control subsystem or central processing unit (CPU) or microprocessor. In some configurations, the memory controller is physically subsumed into the same physical chip as the processor. In other configurations the memory controller may be just one of many logical components comprising a memory controller hub. A memory controller hub typically supports completely separate and distinct memory address spaces, often using different types of semiconductor memory or different purposes. For example, a memory controller may support the use of video DRAM for graphics applications, flash memory for disk-drive acceleration, and commodity DRAM as the processor's main external memory.
The limitations imposed by memory protocols, traditional memory subsystem architectures, standards, processor-specific memory access models, end-user configurability requirements, power constraints, or combinations of those limitations tend to interact in such a manner that reduce performance and result in non-optimal memory subsystems. Recently, Memory Control Hubs (MCHs) have been proposed to enhance memory performance between processors and memory subsystems. However, MCHs are defined primarily as a memory subsystem for a single processor. Many general purpose system architectures include multiple processors, each possibly with their own memory domain. Often these multiple processors need to communicate between themselves. As a result, private processor communication buses have been proposed to enhance system interconnection.
However, the current generation of general purpose system interconnect specifications do not provide sufficient functionality, flexibility and performance necessary to maintain appropriate balance in systems whose main memory is based upon high bandwidth devices such as are proposed with the HMC specification. It is often the case to find system architectures that maintain many hundreds of gigabytes per second of access to local memory bandwidth, but provide a small fraction (on the order of 1/10th) of this bandwidth to the system interconnect. This result is a highly imbalanced system.
This phenomenon is especially evident in applications with multiple threads (e.g., tasks) of execution distributed among multiple processing sockets/devices. If the core processor supports functional data caching, the cache coherency mechanism that must be present between the processor sockets must support a local memory bandwidth that may be an order of magnitude larger than the bandwidth on the system interconnect. The result is a highly imbalanced system.
There is a need for interconnect systems and methodologies that provide more balanced system bandwidth and can also reduce the complexity needed to design such interconnect systems.